1. Field of the Invention
The present invention relates to a solid-state imaging device and more particularly, to a two-dimensional solid-state imaging device that prevents transmission errors during a signal-charge transfer process from vertical charge-transfer sections to a horizontal charge-transfer section, and a fabrication method of the device.
2. Description of the Prior Art
FIG. 1 schematically shows a plan view of one of photoelectric conversion sections and its neighborhood of a conventional two-dimensional solid-state imaging device of the progressive-scan interline-transfer type. FIGS. 2 and 3 schematically show cross-sectional views along the lines II--II and III--III in FIG. 1, respectively. FIG. 4 schematically shows a plan view of an interconnection area between one of single-channel vertical charge-transfer sections and a single-channel horizontal charge-transfer section. FIGS. 5 and 6 schematically show cross-sectional views along the lines V--V and VI--VI in FIG. 4, respectively.
As shown in FIGS. 1 and 4, rectangular photoelectric conversion sections 151 are arranged in a matrix array. Elongated vertical charge-transfer sections 152 are arranged along the respective columns of the matrix array. An elongated horizontal charge-transfer section 153 is disposed at the output-side ends of the vertical charge-transfer sections 152 to extend along the rows of the matrix array. An output section, which is disposed at the output-side end of the horizontal charge-transfer section 153, is not shown here.
Each of the vertical charge-transfer sections 152 is formed by a vertical Charge-Coupled Device (CCD) register. The horizontal charge-transfer section 153 is formed by a horizontal CCD register.
As shown in FIGS. 2, 3, 5, and 6, p-type wells 102, 103, and 104 are formed in a surface region of an n-type silicon substrate 101. The elongated p-type well 102 is formed in the horizontal charge-transfer section 153 to extend along the section 153. The rectangular p-type wells 103 are located in the respective photoelectric conversion sections 151. The elongated p-type wells 104 are located in the respective vertical charge-transfer sections 152 to extend along the corresponding sections 152.
The p-type wells 102 in the horizontal charge-transfer section 153 have a depth large enough for preventing the punch-through phenomenon from occurring in source/drain regions of Metal-oxide-Semiconductor Field-Effect Transistors (MOSFETs) provided in the output section. The p-type wells 102 is deeper than the p-type wells 103 and 104. The p-type wells 102 have a doping concentration lower than that of the p-type wells 104 for the purpose of allowing to drive the horizontal charge-transfer section 153 by using a low-voltage and high-frequency driving signal.
The p-type wells 103 in the photoelectric conversion sections 151 have a low doping concentration to allow the so-called "electronic shutter" operation, which is defined as an operation that the signal charges stored in photodiodes 130 in the sections 151 are transferred to the remaining substrate 101 when a specific voltage is applied to the substrate 101.
The p-type wells 104 in the vertical charge-transfer sections 152 have a higher doping concentration than that of the wells 103 so that the signal charges in the vertical charge-transfer sections 152 do not flow into the remaining substrate 101 at the time the electronic shutter operation is performed.
In the photoelectric conversion sections 151, as shown in FIGS. 1 and 2, rectangular n-type diffusion regions 108 are formed in the respective p-type wells 103. Each of the n-type diffusion regions 108 and a corresponding one of the remaining p-type wells 103 constitute the photodiode 130.
In the vertical charge-transfer sections 152, as shown in FIGS. 1 to 3, elongated n-type buried channel regions 105 are formed in the respective p-type wells 104 to extend along the corresponding wells 104.
In the horizontal charge-transfer sections 153, as shown in FIGS. 4 and 5, n-type buried channel regions 106 and 107 are formed in the p-type well 102. The buried channel regions 106 and 107 are alternately arranged along the well 102. The buried channel regions 106 serve as charge-storage regions for storing the signal charges. The buried channel regions 107 serve as charge-barrier regions for confining the signal charges in the adjoining charge-storage regions.
The n-type buried channel regions 106 have a doping concentration slightly greater than that of the n-type buried channel regions 107. The doping concentrations of the n-type buried channel regions 106 and 107, which are determined according to the doping concentration of the corresponding p-type well 102, are less than that of the n-type buried channel regions 105.
P-type diffusion regions 109 and 110 are formed in the surface region of the substrate 101 at the respective interfaces between the p-type wells 103 and 104, as shown in FIG. 2. The p-type diffusion regions 109 serve as channel stops. The p-type diffusion regions 110 serve as parts of read-out gates for transferring the signal charges in the photodiodes 130 to the corresponding vertical charge-transfer sections 152. The p-type diffusion regions 109 have a high doping concentration. The p-type diffusion regions 110 have a low doping concentration.
A gate oxide film 111 is formed on the surface of the substrate 101 to cover the photoelectric conversion sections 151, the vertical charge-transfer sections 152, and the horizontal charge-transfer section 153.
First, second, and third patterned polysilicon films 112, 113, and 114 are formed on the gate oxide film 111 in the photoelectric conversion sections 151 and the vertical and horizontal charge-transfer sections 152 and 153. These polysilicon films 112, 113, and 114 serve as gate electrodes and wiring lines. Parts of the polysilicon films 112, 113, and 114 which are contacted with the gate oxide film 111 serve as the gate electrodes. Parts of the polysilicon films 112, 113, and 114 which are not contacted with the gate oxide film 111 serve as the wiring lines.
The p-type diffusion region 110, the corresponding gate electrode, and the gate oxide film 111 in each of the photoelectric conversion sections 151 constitute the read-out gate. The buried channel region 105, the corresponding gate electrodes, and the gate oxide film 111 in each of the vertical charge-transfer sections 152 constitute the vertical CCD register driven by a four-phase driving signal. The buried channel region 102, the corresponding gate electrodes, and the gate oxide film 111 in the horizontal charge-transfer section 153 constitute the horizontal CCD register driven by a two-phase driving signal.
In the vertical and horizontal charge-transfer sections 152 and 153, the second polysilicon film 113 is partially overlapped with the underlying first polysilicon film 112. Further, the third polysilicon film 114 is partially overlapped with the underlying first and second polysilicon films 112 and 113. The second polysilicon film 113 is electrically insulated from the first polysilicon film 112 by an intervening gate oxide film 111a. The third polysilicon film 114 is electrically insulated from the underlying first polysilicon film 112 by the gate oxide film 111a and from the underlying second polysilicon film 113 by a gate oxide film 111b.
An interlayer insulating film 115 is formed to cover the first, second, and third polysilicon films 112, 113, and 114 in the photoelectric conversion sections 151 and the vertical and horizontal charge-transfer sections 152 and 153.
A metal film 116 is formed on the interlayer insulating film 115 in the photoelectric conversion sections 151 and the vertical and horizontal charge-transfer sections 152 and 153. As shown in FIGS. 1 and 2, the metal film 116 has rectangular windows 116a located in the respective photoelectric conversion sections 151 to allow the incident light to enter the photodiodes 130. The metal film 116 serves as a light shielding film and a wiring line or lines.
A cover oxide film 117 is formed on the metal film 116 in the photoelectric conversion sections 151 and the vertical and horizontal charge-transfer sections 152 and 153 to protect the inner layered structures.
A fabrication method of the above conventional solid-state imaging device is explained below with reference to FIGS. 7A to 7C showing the same cross section as that in FIG. 6.
First, as shown in FIG. 7A, the p-type wells 102, which are located in the horizontal charge-transfer section 153, are formed in the surface region of the n-type silicon substrate 101. Then, the p-type wells 103, which are located in the photoelectric conversion sections 151, are formed in the surface region of the substrate 101. Further, the p-type wells 104, which are located in the vertical charge-transfer sections 152, are formed in the surface region of the substrate 101.
Subsequently, phosphorus (P) ions are selectively implanted into the p-type wells 103 as an n-type impurity, forming the n-type diffusion regions 108 in the photoelectric conversion regions 151. Boron (B) ions are selectively implanted into the interfaces between the p-type wells 103 and 104 and their neighborhood as a p-type impurity, forming the p-type channel stop regions 109 and the p-type read-out gate regions 110.
Next, phosphorus ions are selectively implanted into the p-type wells 104 and 102 in the vertical and horizontal charge-transfer sections 152 and 153, forming an n-type region 106' in the vertical and horizontal charge-transfer sections 152 and 153. The state at this stage is shown in FIG. 7A.
After a patterned resist film 118 uncovering the vertical charge-transfer sections 152 only is formed on the substrate 101, phosphorus ions are selectively implanted into the n-type region 106' again using the resist film 118 as a mask, forming the n-type buried channel regions 105 having the doping concentration greater than that of the remaining n-type region 106' in the vertical charge-transfer sections 152, as shown in FIG. 7B. The resist film 118 is then removed.
The resist film 118 is designed so that the interface 120 between each of the n-type buried channel regions 105 and the remaining n-type region 106' is located just below a corresponding end 112a of the polysilicon film 112 near the interface between the vertical charge-transfer sections 151 and the horizontal charge-transfer section 152.
Following this, the gate oxide film 111 is formed on the substrate 101 to cover the photoelectric conversion sections 151 and the vertical and horizontal charge-transfer sections 152 and 153, as shown in FIG. 7C.
The first patterned polysilicon film 112 is then formed on the gate oxide film 111. The first polysilicon film 112 serves as the gate electrodes for applying one of the four driving voltages to the vertical CCD registers in the vertical charge-transfer sections 152 and the gate electrodes for applying one of the two driving voltages to the horizontal CCD register in the horizontal charge-transfer section 153. These gate electrodes in the horizontal charge-transfer section 153 are located on the n-type buried channel regions 106 serving as the charge-storage regions.
Moreover, a patterned resist film (not shown) uncovering the horizontal charge-transfer section 153 only is formed on the gate oxide film 111. Then, boron ions are selectively implanted into the remaining n-type region 106' again to decrease the doping concentration using the resist film and the polysilicon film 112 as a mask, forming the n-type buried channel regions 107. The non-implanted parts of the remaining n-type region 106' during this process constitute the n-type buried channel regions 106. The n-type buried channel regions 106 and 107 are alternately arranged along the horizontal charge-transfer section 153.
Since the boron ions as a p-type impurity are implanted into the remaining n-type region 106', the n-type buried channel regions 106 serving as the charge-storage regions are greater in doping concentration than the n-type buried channel regions 107 serving as the charge-barrier regions.
Subsequently, the gate oxide film 111a is selectively formed on the surface of the first polysilicon film 112, and then, the second patterned polysilicon film 113 is formed on the gate oxide films 111 and 111a, as clearly shown in FIGS. 3, 5, and 6. The second patterned polysilicon film 113 serves as the gate electrodes for applying remaining two ones of the four driving voltages to the vertical CCD registers in the vertical charge-transfer sections 152 and the gate electrodes for applying another one of the two driving voltages to the horizontal CCD register in the horizontal charge-transfer section 153. These gate electrodes in the horizontal charge-transfer section 153 are located on the n-type buried channel regions 107 serving as the charge-barrier regions.
The gate oxide film 111b is selectively formed on the surface of the second polysilicon film 113, and then, the third patterned polysilicon film 114 is formed on the gate oxide films 111, 111a, and 111b, as clearly shown in FIGS. 2, 3, 5, and 6. The third patterned polysilicon film 114 serves as the gate electrodes for applying the remaining one of the four driving voltages to the vertical CCD registers in the vertical charge-transfer sections 152 and the read-out gates in the photoelectric conversion section 151.
Following this step, the interlayer insulating film 115 is formed to cover the photoelectric conversion section 151 and the vertical and horizontal charge-transfer sections 152 and 153. The metal film 116 serving as the light-shield and the wiring line is formed on the interlayer insulating film 115. The cover oxide film 117 is formed on the metal film 116.
Thus, the conventional solid-state imaging device shown in FIGS. 1 to 6 is fabricated.
The conventional solid-state imaging device has the following problem.
Specifically, the interfaces 120 between the n-type buried channel regions 105 and 106 are defined by using the resist film 118 during the boron-ion-implantation process shown in FIG. 7C. Also, the n-type buried channel regions 107 are formed by a subsequent boron-ion-implantation process using the first polysilicon film 112 as a mask. Therefore, as shown in FIG. 7C, the interfaces 121 and 122 of the region 107 located at the interconnection area of each of the vertical charge-transfer sections 152 and the horizontal charge-transfer section 153 tends to fluctuate. This fluctuation is caused by (a) the placement error of the resist film 120 for the phosphorus-ion-implantation process shown in FIG. 7B, (b) the overlay error of the resist film for the first polysilicon film 112 shown in FIG. 7B, and (c) the dimension error of the first polysilicon film 112 during the etching or patterning process.
For example, when the interfaces 120 are shifted to be located below the first polysilicon film 112, as shown in FIG. 6, n-type regions 106" are formed between the respective n-type buried channel regions 105 and 107. In this case, the n-type regions 106, 107, 106", and 105 have an electric potential as shown in FIG. 8. In FIG. 8, H.sub.1 and H.sub.2 are the two-phase driving voltages for the horizontal charge-transfer section 153 and V.sub.1 and V.sub.2 are two ones of the four-phase driving voltages for the vertical charge-transfer sections 152. The points P1, P2, P3, P4, and P5 are defined as shown in FIG. 6.
It is seen from FIG. 8 that a potential barrier having a potential difference .DELTA..phi.3 is generated in the n-type region 106" between the points P2 and P3.
On the other hand, when the interfaces 120 are shifted to be located below the windows of the first polysilicon film 112, as shown in FIG. 9, n-type regions 105' are formed between the respective n-type buried channel regions 105 and 107. The n-type regions 106, 107, 105', and 105 have an electric potential as shown in FIG. 10.
It is seen from FIG. 10 that a potential dip having a potential difference .DELTA..phi.2 is generated in the n-type region 105' between the points P2 and P3.
The above potential barrier and dip will cause some transfer error of the signal charges during the transfer process from the vertical charge-transfer sections 152 to the horizontal charge-transfer section 153.